The behaviour of systems on chip (soc) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC). Debugging such socs is hard. Based on a classification of debug scope and granularity, we propose that debugging should be communication-centric and based on transactions. Communication-centric debug focusses on the communication and the synchronisation between the IP blocks, which are implemented by the interconnect using transactions. We define and implement a modular debug architecture, based on NOC, monitors, and a dedicated high-speed event-distribution broadcast interconnect. The manufacturing-test scan chains and IEEE1149.1 test access ports (TAP) are re-used for configuration and debug data read-out. Our debug architecture requires only small changes to the functional architecture. The additional area cost is limited to the monitors and the event distribution interconnect, which are 4.5% of the NOC area, or less than 0.2% of the SOC area. The debug architecture runs at NOC functional speed and reacts very quickly to debug events to stop the soc close in time to the condition that raised the event. The speed at which data is retrieved from the soc after stopping using the TAP is 10 MHz. We prove our concepts and architecture with a gate-level implementation that includes the NOC, event distribution interconnect, and clock, reset, and TAP controllers. We include gate-level signal traces illustrating debug at message and transaction levels. © 2007 IEEE.
|Title of host publication||NOCS 2007: First International Symposium on Networks-on-Chip, 7 May 2007 through 9 May 2007, Princeton, NJ|
|Publication status||Published - 2007|