Top-down design and verification methodology for analog mixed-signal integrated circuits

P. Beviz

Research output: ThesisPd Eng Thesis

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The current report contains the introduction of a novel Top-Down Design and Verification methodology for AMS integrated circuits. With the introduction of new design and verification flow, more reliable and efficient development of AMS ICs is possible. The assignment incorporated the research on the field of chip design, the analysis of the currently applied design flow at NXP. Moreover, the report proposes the necessary changes to step-up for the standardized top-down design flow. The project imple-mented the novel design methodology with the integration of SystemC and SystemC-AMS system-level modeling languages, COSIDE IDE and NXP`s SystemIntegrator. The flow supports the possibility of con-current design and verification to speed up the design process. In order to realize early IP and system-level verification in the product lifecycle, the concept of executable descriptions were introduced in this report. Furthermore, the feasibility of the top-down flow was proved via the implementation of TJA1146 CAN transceiver based pilot project. The report ends with the conclusion of the designed process and recommendations for future work.
Original languageEnglish
  • Heuberger, Peter, Supervisor
  • Schmaltz, Julien, Supervisor
  • Grimbergen, S.P., External supervisor, External person
  • Oosterhuis, M.W.M., External supervisor, External person
Award date29 Sep 2016
Place of PublicationEindhoven
Publication statusPublished - 29 Sep 2016

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