In this paper, a timing speculation technique with low-overhead in situ delay monitors placed along critical paths is presented. The proposed insertion of monitors enables timing error prevention within the same clock cycle. Compared to other techniques, the design cost per monitor in our technique is low because no additional gates for the guard banding, inspection window generation, and short path extension are required. We benchmarked our approach on an ARM Cortex M0. The insertion strategy reduces the number of monitors by up to\sim 23\times , power by\sim 5.5\times , and area by\sim 2.8\times compared to the traditional in situ monitoring techniques that insert monitors at the flip-flops. The timing error correction uses a global clock stretching unit to prevent errors within one cycle. With the proposed error prevention technique, 22% more delay variation is tolerated with a negligible energy overhead of less than 1%.
|Number of pages||12|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 1 May 2019|
- In situ delay monitoring
- Timing error
- Timing speculation (ts)
- Variation resilience