Timing error measurement for highly linear wideband digital to analog converters

E. Bechthum; Y. Tang; J.A. Hegt; A.H.M. Roermund, van

doi:10.1109/ISCAS.2011.5937992

Timing error measurement for highly linear wideband digital to analog converters

E. Bechthum, Y. Tang, J.A. Hegt, A.H.M. Roermund, van

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

160 Downloads (Pure)

Abstract

The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

Original language	English
Title of host publication	Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	0271-4302
ISBN (Print)	978-1-4244-9472-9
DOIs	https://doi.org/10.1109/ISCAS.2011.5937992
Publication status	Published - 2011

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Bechthum, E., Tang, Y., Hegt, J. A., & Roermund, van, A. H. M. (2011). Timing error measurement for highly linear wideband digital to analog converters. In Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil (pp. 0271-4302). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2011.5937992

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title = "Timing error measurement for highly linear wideband digital to analog converters",

abstract = "The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.",

author = "E. Bechthum and Y. Tang and J.A. Hegt and {Roermund, van}, A.H.M.",

year = "2011",

doi = "10.1109/ISCAS.2011.5937992",

language = "English",

isbn = "978-1-4244-9472-9",

pages = "0271--4302",

booktitle = "Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil",

publisher = "Institute of Electrical and Electronics Engineers",

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Bechthum, E, Tang, Y, Hegt, JA & Roermund, van, AHM 2011, Timing error measurement for highly linear wideband digital to analog converters. in Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil. Institute of Electrical and Electronics Engineers, Piscataway, pp. 0271-4302. https://doi.org/10.1109/ISCAS.2011.5937992

Timing error measurement for highly linear wideband digital to analog converters. / Bechthum, E.; Tang, Y.; Hegt, J.A. et al.
Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 0271-4302.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

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Timing error measurement for highly linear wideband digital to analog converters

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