The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds . Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical. A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.
|Title of host publication||Proceedings of the 2011 international symposium on circuits and systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2011|