Time-interleaved SAR and slope converters

P.J.A. Harpe, M. Ding, B. Büsze, C. Zhou, K.J.P. Philips, H.W.H. Groot, de

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This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures. At the same time, complex calibration schemes are not required thanks to their inherent accuracy. The architectures are examined and compared, circuit implementations and measurement results are discussed and an outlook to the future will be given.
Original languageEnglish
Title of host publicationProceedings of the 21st Workshop on Advances in Analog Circuit Design, AACD 2012, 27-29 March 2012, Valkenburg, The Netherlands
Place of PublicationBerlin
Publication statusPublished - 2012
Eventconference; AACD 2012 Workshop -
Duration: 1 Jan 2012 → …


Conferenceconference; AACD 2012 Workshop
Period1/01/12 → …
OtherAACD 2012 Workshop


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