Abstract
Time-Interleaved ADCs are essential for new generation mm-wave digital beamforming receivers offering multi-GHz bandwidths for radar sensing or high data rate communication links. Timing mismatches is one of the main performance limitations of these ADCs. Especially for large beamforming arrays they can become bottleneck for system power and area when corrected with digital filtering techniques at GHz rates. This work analyzes timing errors in digital beamforming receivers and introduces a novel correction algorithm that takes advantage of the array of ADCs and the beamforming function together. The proposed algorithm suppresses significantly the impact from timing mismatches with low complexity enabling major power savings for massive digital beamforming arrays.
Original language | English |
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Title of host publication | 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1-5 |
Number of pages | 5 |
ISBN (Electronic) | 978-1-7281-9201-7 |
ISBN (Print) | 978-1-7281-9202-4 |
DOIs | |
Publication status | Published - 27 Apr 2021 |
Event | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - VIRTUAL, Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021 |
Conference
Conference | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 |
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Country/Territory | Korea, Republic of |
City | Daegu |
Period | 22/05/21 → 28/05/21 |
Keywords
- digital beamforming
- ADC
- Time Interleave
- Mismatch correction