Threshold voltage and power-supply tolerance of CMOS logic design families

The advent of deep submicron technologies brings new challenges to digital circuit design. A reduced threshold voltage (VT) and power supply (Vdd) in addition to process variabilities have a direct impact on circuit design. In a semiconductor environment it is conventionally thought that parametric yield is high and stable and that the main yield losses are functional. Although functional yield remains the main focus of attention, modern and future circuits may not have the presumed high parametric yield. We present a study that compares the tolerance to process variability of various design families for metrics including timing and power consumption under VT-Vdd scalability using a NAND gate as a test vehicle. Basically, the fundamental limitations to the scaling of the supply voltage due to the statistical variation of MOS VT are investigated and defined. The four logic families under study are: static CMOS, Differential Complementary Voltage Swing Logic (DCVSL), Domino and Pass Logic