The neutral-point clamped, flying-capacitor and cascaded H-bridge converter topologies are examples of multilevel topologies in which switch devices are connected in series. One of the advantages of this series connection is that the supply voltage is distributed over the switch devices, reducing its stress. Although the topologies are creating a multilevel waveform at the output side, at the dc input-voltage side, however, these series-type converter topologies are still creating a two-level rectangular-wave input current producing harmonic distortion which is undesired in applications where the converter is directly connected to a dc grid. Interleaved topologies, on the other hand, are characterized by switches connected in parallel, resulting in the property that current is equally distributed over the switch devices. Additionally, the interleaved topology has the advantage of creating multilevel output voltage as well as creating multilevel input current. Therefore, a circuit which has this property of the interleaved converter and is characterized by switch devices in series will result in a desirable topology and may be useful in many applications. This paper performs a theoretical analysis of the duality principle and applies it to the interleaved topology, resulting in the interleaved-dual topology, a series topology with the same property as the interleaved topology. Simulation results are presented to show the dual multilevel behavior.
|Title of host publication||Proceedings of the 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 18-21 May 2014, Hiroshima, Japan|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2014|
Caris, M. L. A., Huisman, H., & Duarte, J. L. (2014). Theoretical analysis of the duality principle applied to interleaved topologies. In Proceedings of the 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 18-21 May 2014, Hiroshima, Japan (pp. 2954-2959). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IPEC.2014.6870103