The influence of polysilicon gate morphology on dopant activation and deactivation kinetics in deep-submicron CMOS transistors

F.N. Cubaynes, P.A. Stolk, J. Verhoeven, F. Roozeboom, P.H. Woerlee

Research output: Contribution to journalArticleAcademicpeer-review

18 Citations (Scopus)

Abstract

In this paper, the impact of gate microstructure on the activation and deactivation kinetics of ion-implanted dopants is discussed. A comparison is made between large-grained polysilicon that was obtained by recrystallizing deposited amorphous silicon, and fine-grained polysilicon. Very good gate activation was achieved for both As- and B-implanted fine-grained polysilicon gates using post-implant rapid thermal annealing for 20 s at 980-1010°C, leading to gate depletion levels below 5%. Similar levels of gate activation are found for spike annealing of 1 s at 1100°C. The kinetics of dopant deactivation in large- and fine-grained polysilicon have been measured in the temperature range from 700 to 800°C. From these measurements, the loss in the gate activation due to extra annealing steps in a 0.13 μm CMOS process flow has been evaluated. Silicidation is the most harmful process step leading to an increase in the gate depletion level to 6% for a p-type fine-grained polysilicon gate, representing the worst case situation. Finally, TSUPREM-4 gate depletion simulations for future CMOS generations (≤0.10 μm) have revealed the need of high dopant concentration (4-5 × 1020 cm-3) which questions the possibility of polysilicon use as a gate material.

Original languageEnglish
Pages (from-to)351-356
Number of pages6
JournalMaterials Science in Semiconductor Processing
Volume4
Issue number4
DOIs
Publication statusPublished - 1 Aug 2001
Externally publishedYes

Keywords

  • Amorphous silicon
  • Boron penetration
  • Gate deactivation
  • Gate depletion
  • Hall effect
  • Polysilicon
  • Spike annealing

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