Using discrete time process algebra with relative timing, a model for the I2C-bus is designed. The model of the I2C-bus is divided into three parts: a model for the bus lines, a model for the master interfaces and a model for the slave interfaces. The model of the bus lines is based on a model for a wired-AND. For the models of the interfaces, the approach is to start from a high level bus protocol and refine it step by step. First, a single master without timing constraints is considered. Then the model is adapted to deal with the timing constraints. Then also the restriction to a single master is relaxed. It turns out that the model for the slave interfaces can be based on the model for the master interfaces. The use of the model obtained is discussed and illustrated.