Abstract
The design and critical parts of the modelling of a monolithic 8-bit 100 megasamples per second folding type analog-to-digital converter is reported. This system will be implemented in an advanced bipolar HSIII process. Distributed models for resistors and transistors appear to be better approximations for measured data than single transistor and resistor models. The error introduced by differential delays is an important error source in very high-speed analog-to-digital converters. A simple behavior model is used to describe this delay. Simulation results indicate that a folding type analog-to-digital converter can achieve a performance comparable to or even exceeding flash converters while using only a fraction of the die area and power.
| Original language | English |
|---|---|
| Article number | R1168 |
| Pages (from-to) | 482-509 |
| Number of pages | 29 |
| Journal | Philips Journal of Research |
| Volume | 42 |
| Issue number | 5-6 |
| Publication status | Published - 1 Dec 1987 |
| Externally published | Yes |
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The design of an 8-bit folding analog-to-digital converter. / van de Plassche, R.; Baltus, P.
In: Philips Journal of Research, Vol. 42, No. 5-6, R1168, 01.12.1987, p. 482-509.Research output: Contribution to journal › Article › Academic › peer-review
TY - JOUR
T1 - The design of an 8-bit folding analog-to-digital converter
AU - van de Plassche, R.
AU - Baltus, P.
PY - 1987/12/1
Y1 - 1987/12/1
N2 - The design and critical parts of the modelling of a monolithic 8-bit 100 megasamples per second folding type analog-to-digital converter is reported. This system will be implemented in an advanced bipolar HSIII process. Distributed models for resistors and transistors appear to be better approximations for measured data than single transistor and resistor models. The error introduced by differential delays is an important error source in very high-speed analog-to-digital converters. A simple behavior model is used to describe this delay. Simulation results indicate that a folding type analog-to-digital converter can achieve a performance comparable to or even exceeding flash converters while using only a fraction of the die area and power.
AB - The design and critical parts of the modelling of a monolithic 8-bit 100 megasamples per second folding type analog-to-digital converter is reported. This system will be implemented in an advanced bipolar HSIII process. Distributed models for resistors and transistors appear to be better approximations for measured data than single transistor and resistor models. The error introduced by differential delays is an important error source in very high-speed analog-to-digital converters. A simple behavior model is used to describe this delay. Simulation results indicate that a folding type analog-to-digital converter can achieve a performance comparable to or even exceeding flash converters while using only a fraction of the die area and power.
UR - http://www.scopus.com/inward/record.url?scp=0023595749&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0023595749
VL - 42
SP - 482
EP - 509
JO - Philips Journal of Research
JF - Philips Journal of Research
SN - 0165-5817
IS - 5-6
M1 - R1168
ER -