The design of an 8-bit folding analog-to-digital converter

The design and critical parts of the modelling of a monolithic 8-bit 100 megasamples per second folding type analog-to-digital converter is reported. This system will be implemented in an advanced bipolar HSIII process. Distributed models for resistors and transistors appear to be better approximations for measured data than single transistor and resistor models. The error introduced by differential delays is an important error source in very high-speed analog-to-digital converters. A simple behavior model is used to describe this delay. Simulation results indicate that a folding type analog-to-digital converter can achieve a performance comparable to or even exceeding flash converters while using only a fraction of the die area and power.