The design of an 8-bit folding analog-to-digital converter

R. van de Plassche, P. Baltus

Research output: Contribution to journalArticleAcademicpeer-review

1 Citation (Scopus)

Abstract

The design and critical parts of the modelling of a monolithic 8-bit 100 megasamples per second folding type analog-to-digital converter is reported. This system will be implemented in an advanced bipolar HSIII process. Distributed models for resistors and transistors appear to be better approximations for measured data than single transistor and resistor models. The error introduced by differential delays is an important error source in very high-speed analog-to-digital converters. A simple behavior model is used to describe this delay. Simulation results indicate that a folding type analog-to-digital converter can achieve a performance comparable to or even exceeding flash converters while using only a fraction of the die area and power.

Original languageEnglish
Article numberR1168
Pages (from-to)482-509
Number of pages29
JournalPhilips Journal of Research
Volume42
Issue number5-6
Publication statusPublished - 1 Dec 1987
Externally publishedYes

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Digital to analog conversion
Resistors
Transistors

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van de Plassche, R. ; Baltus, P. / The design of an 8-bit folding analog-to-digital converter. In: Philips Journal of Research. 1987 ; Vol. 42, No. 5-6. pp. 482-509.
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van de Plassche, R & Baltus, P 1987, 'The design of an 8-bit folding analog-to-digital converter', Philips Journal of Research, vol. 42, no. 5-6, R1168, pp. 482-509.

The design of an 8-bit folding analog-to-digital converter. / van de Plassche, R.; Baltus, P.

In: Philips Journal of Research, Vol. 42, No. 5-6, R1168, 01.12.1987, p. 482-509.

Research output: Contribution to journalArticleAcademicpeer-review

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