Designing a SoC for applications with mixed time-criticality is a complex and time-consuming task. Even when SoCs are built from components with known real-time properties, they still have to be combined and configured correctly to assert that these properties hold for the complete system, which is non trivial. Furthermore, applications need to be mapped to the available hardware resources and correctly integrated with the SoC's software stack, such that the realtime requirements of the applications are guaranteed to be satisfied. However, as systems grow in complexity, the design and verification effort increases, which makes it difficult to satisfy the tight time-to-market constraint. Design tools are essential to speed up the development process and increase profit. This paper presents the design flow for the CompSOC FPGA platform: a template for SoCs with mixed time-criticality applications. This work outlines how the development time of such a platform instance is reduced by means of its comprehensive tool flow, that aids a system designer in creating hardware, the associated software stack, and application mapping. Copyright 2013 ACM.
|Title of host publication||Proceedings of the 10th FPGAworld Conference, (FPGAworld 2013), 10 - 12 September 2013 , Stockholm, Sweden|
|Place of Publication||New York|
|Publisher||Association for Computing Machinery, Inc|
|Publication status||Published - 2013|
Goossens, S. L. M., Akesson, K. B., Koedam, M. L. P. J., Nejad, A. B., Nelson, A., & Goossens, K. G. W. (2013). The CompSOC design flow for virtual execution platforms. In Proceedings of the 10th FPGAworld Conference, (FPGAworld 2013), 10 - 12 September 2013 , Stockholm, Sweden (pp. 7-1/6). Association for Computing Machinery, Inc. https://doi.org/10.1145/2513683.2513690