The analysis of spot defect induced faults in MOS circuits

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Abstract

A strategy for modeling spot defect induced faults by their corresponding Boolean functions is developed. The presented strategy is based on the principle of local conduction path analysis. This way of modeling is much more general in the sense that all kinds of faults are unified by one concept, the Boolean function. In this way testing related applications can be done efficiently and can maintain a high quality
Original languageEnglish
Title of host publicationProceedings of the 1991 International Conference on Circuits and Systems, 16-17 June 1991, Shenzhen, China
Place of PublicationNew York
PublisherInstitute of Electrical and Electronics Engineers
Pages478-481
DOIs
Publication statusPublished - 1991

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