Abstract
To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during
its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient.
The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias
(TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new
generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In
addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes
and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing
3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level
probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.
its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient.
The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias
(TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new
generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In
addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes
and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing
3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level
probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.
| Original language | English |
|---|---|
| Title of host publication | 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) |
| Place of Publication | PIscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1689-1694 |
| ISBN (Electronic) | 978-3-9810801-6-2 |
| ISBN (Print) | 978-1-4244-7054-9 |
| Publication status | Published - Mar 2010 |
| Externally published | Yes |
| Event | 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) - ICC, Dresden, Germany Duration: 8 Mar 2010 → 12 Mar 2010 Conference number: 13 https://www.date-conference.com/date10/ |
Conference
| Conference | 13th Design, Automation and Test in Europe Conference and Exhibition (DATE 2010) |
|---|---|
| Abbreviated title | DATE 2010 |
| Country/Territory | Germany |
| City | Dresden |
| Period | 8/03/10 → 12/03/10 |
| Other | |
| Internet address |