Testing and diagnosis of power switches in SOCs

S.K. Goel, M. Meijer, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

30 Citations (Scopus)
195 Downloads (Pure)


The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., one or more parts of the SOC can be powered-off during standby mode leading in this way to savings in the overall SOCs power consumption. In this paper, we present a circuit and a method to test power switches. The proposed method allows testing of on/off functionality. In case of segmented power switches individual failing segments can be identified as well by using the proposed test strategy. The method requires only a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead
Original languageEnglish
Title of host publicationProceedings of the Eleventh IEEE European Test Symposium, 2006, ETS '06, 21-24 May 2006, Southampton, United Kingdom
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)0-7695-2566-0
Publication statusPublished - 2006


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