Testing 3D chips containing through-silicon vias

E.J. Marinissen; Y. Zorian

doi:10.1109/TEST.2009.5355573

Testing 3D chips containing through-silicon vias

E.J. Marinissen, Y. Zorian

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

272 Citations (Scopus)

431 Downloads (Pure)

Abstract

Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

Original language	English
Title of host publication	2009 International Test Conference
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	11
ISBN (Print)	978-1-4244-4868-5
DOIs	https://doi.org/10.1109/TEST.2009.5355573
Publication status	Published - Nov 2009
Externally published	Yes
Event	2009 International Test Conference (ITC 2009) - Austin, United States Duration: 1 Nov 2009 → 6 Nov 2009

Conference

Conference	2009 International Test Conference (ITC 2009)
Abbreviated title	ITC 2009
Country/Territory	United States
City	Austin
Period	1/11/09 → 6/11/09

Access to Document

10.1109/TEST.2009.5355573

itc09embtutFinal author version , 508 KB

Cite this

@inbook{f581b4c1737d4a1ca1540934ad99c72f,

title = "Testing 3D chips containing through-silicon vias",

abstract = "Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.",

author = "E.J. Marinissen and Y. Zorian",

year = "2009",

month = nov,

doi = "10.1109/TEST.2009.5355573",

language = "English",

isbn = "978-1-4244-4868-5",

booktitle = "2009 International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2009 International Test Conference (ITC 2009), ITC 2009 ; Conference date: 01-11-2009 Through 06-11-2009",

}

TY - CHAP

T1 - Testing 3D chips containing through-silicon vias

AU - Marinissen, E.J.

AU - Zorian, Y.

PY - 2009/11

Y1 - 2009/11

N2 - Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

AB - Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

U2 - 10.1109/TEST.2009.5355573

DO - 10.1109/TEST.2009.5355573

M3 - Chapter

SN - 978-1-4244-4868-5

BT - 2009 International Test Conference

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2009 International Test Conference (ITC 2009)

Y2 - 1 November 2009 through 6 November 2009

ER -

Testing 3D chips containing through-silicon vias

Abstract

Conference

Access to Document

Fingerprint

Cite this