Testing 3D chips containing through-silicon vias

E.J. Marinissen, Y. Zorian

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

267 Citations (Scopus)
295 Downloads (Pure)


Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
Original languageEnglish
Title of host publication2009 International Test Conference
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages11
ISBN (Print)978-1-4244-4868-5
Publication statusPublished - Nov 2009
Externally publishedYes
Event2009 International Test Conference (ITC 2009) - Austin, United States
Duration: 1 Nov 20096 Nov 2009


Conference2009 International Test Conference (ITC 2009)
Abbreviated titleITC 2009
Country/TerritoryUnited States


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