Test resource management and scheduling for modular manufacturing test of SOCS

S.K. Goel, E.J. Marinissen

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Abstract

This chapter deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC, with specified parameters of modules and their tests, we design an architecture which minimizes the required tester vector memory depth and test application time. In this chapter, we formulate the problem of test architecture design. Subsequently, we derive a formulation of an architecture-independent lower bound for the SOC test time. We present a heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. Experimental results for the ITC’02 SOC Test Benchmarks show that, compared to manual best-effort engineering approaches used in Philips, we can save up to 75% in test times, while compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
Original languageEnglish
Title of host publicationAlgorithms in ambient intelligence
EditorsW.F.J. Verhaegh, E.H.L. Aarts, J.H.M. Korst
Place of PublicationDordrecht
PublisherKluwer Academic Publishers
Chapter17
Pages311-336
ISBN (Print)1-4020-1757-X
DOIs
Publication statusPublished - 2004
Externally publishedYes

Publication series

NamePhilips Research Book Series
Number2

Keywords

  • SOC test
  • TAM and wrapper design
  • lower bound
  • test scheduling
  • idle bits

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