Test cost analysis for 3D die-to-wafer stacking

M. Taouil, S. Hamdioui, K. Beenakker, E.J. Marinissen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

52 Citations (Scopus)
16 Downloads (Pure)


The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), a technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D2W) stacking seems the most favorable approach, due to the ability of Known Good Die stacking. Minimizing the test cost for such a stacking approach is a challenging task. Every manufactured chip has to be tested, and any tiny test saving per 3D-SIC impacts the overall cost, especially in high-volume production. This paper establishes a cost model for D2W SICs and investigates the impact of the test cost for different test flows. It first introduces a framework covering different test flows for 3D D2W ICs. Subsequently, it proposes a test cost model to estimate the impact of the test flow on the overall 3D-SIC cost. Our simulation results show that (a) test flows with pre-bond testing significantly reduce the overall cost, (b) a cheaper test flow does not necessary result in lower overall cost, (c) test flows with intermediate tests (performed during the stacking process) pay off, (d) the most cost-effective test flow consists of pre-bond tests and strongly depends on the stack yield, hence, adapting the test according the stack yield is the best approach to use.
Original languageEnglish
Title of host publication19th IEEE Asian Test Symposium (ATS), 2010 1-4 December 2010
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4244-8841-4
Publication statusPublished - Dec 2010
Externally publishedYes
Event19th IEEE Asian Test Symposium (ATS 2010) - Shanghai, China
Duration: 1 Dec 20104 Dec 2010
Conference number: 19


Conference19th IEEE Asian Test Symposium (ATS 2010)
Abbreviated titleATS
Internet address


  • 3D test flow 3D test cost
  • Die-to-Wafer stacking
  • 3D manufacturing cost
  • Through-Silicon-Via


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