Abstract
According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.
| Original language | English |
|---|---|
| Patent number | US2007208970 |
| IPC | G01R 31/ 3185 A I |
| Priority date | 13/01/05 |
| Publication status | Published - 6 Sept 2007 |
| Externally published | Yes |