Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study

Sandeep K. Goel, Saman Adham, Min-Jer Wang, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Erik Jan Marinissen

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Abstract

TSMC has developed the Chip‐on‐Wafer‐on‐Substrate (CoWoS®) process as a design paradigm to assemble silicon interposer‐based 3D‐ICs. To reach quality requirements for volume production, several test challenges related to 3D‐ICs need to be addressed. This chapter describes the test and diagnosis solutions for the challenges that were faced in designing a CoWoS® process‐based heterogeneous memory‐on‐logic and logic‐on‐logic 3D‐IC. The objective of this design was to find the stacking process weaknesses in creating a stacked die system consisting of multiple dies in different technologies (logic and memory). It is also used to demonstrate the strength of the stacking capability when dies to be stacked are sourced from different vendors. The design contains three dies: system‐on‐chip die (logic), DRAM die (logic), and JEDEC WideIO DRAM die (memory). The chapter demonstrates how the design‐for‐diagnosis features implemented on the logic die were used to isolate interconnect testing failures.
Original languageEnglish
Title of host publicationHandbook of 3D integration
Subtitle of host publicationvolume 4: design, test, and thermal management
EditorsP.D. Franzon, E.J. Marinissen, M.S. Bakir
Place of PublicationWeinheim
PublisherWiley-VCH Verlag
Chapter15
Pages325-346
Number of pages22
ISBN (Print)978-3-527-33855-9
DOIs
Publication statusPublished - 8 Feb 2019

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Goel, S. K., Adham, S., Wang, M-J., Lee, F., Chickermane, V., Keller, B. L., ... Marinissen, E. J. (2019). Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study. In P. D. Franzon, E. J. Marinissen, & M. S. Bakir (Eds.), Handbook of 3D integration: volume 4: design, test, and thermal management (pp. 325-346). Weinheim: Wiley-VCH Verlag. https://doi.org/10.1002/9783527697052.ch15
Goel, Sandeep K. ; Adham, Saman ; Wang, Min-Jer ; Lee, Frank ; Chickermane, Vivek ; Keller, Brion L. ; Valind, Thomas ; Marinissen, Erik Jan. / Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study. Handbook of 3D integration: volume 4: design, test, and thermal management. editor / P.D. Franzon ; E.J. Marinissen ; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. pp. 325-346
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Goel, SK, Adham, S, Wang, M-J, Lee, F, Chickermane, V, Keller, BL, Valind, T & Marinissen, EJ 2019, Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study. in PD Franzon, EJ Marinissen & MS Bakir (eds), Handbook of 3D integration: volume 4: design, test, and thermal management. Wiley-VCH Verlag, Weinheim, pp. 325-346. https://doi.org/10.1002/9783527697052.ch15

Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study. / Goel, Sandeep K.; Adham, Saman; Wang, Min-Jer; Lee, Frank; Chickermane, Vivek; Keller, Brion L.; Valind, Thomas; Marinissen, Erik Jan.

Handbook of 3D integration: volume 4: design, test, and thermal management. ed. / P.D. Franzon; E.J. Marinissen; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. p. 325-346.

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

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AB - TSMC has developed the Chip‐on‐Wafer‐on‐Substrate (CoWoS®) process as a design paradigm to assemble silicon interposer‐based 3D‐ICs. To reach quality requirements for volume production, several test challenges related to 3D‐ICs need to be addressed. This chapter describes the test and diagnosis solutions for the challenges that were faced in designing a CoWoS® process‐based heterogeneous memory‐on‐logic and logic‐on‐logic 3D‐IC. The objective of this design was to find the stacking process weaknesses in creating a stacked die system consisting of multiple dies in different technologies (logic and memory). It is also used to demonstrate the strength of the stacking capability when dies to be stacked are sourced from different vendors. The design contains three dies: system‐on‐chip die (logic), DRAM die (logic), and JEDEC WideIO DRAM die (memory). The chapter demonstrates how the design‐for‐diagnosis features implemented on the logic die were used to isolate interconnect testing failures.

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Goel SK, Adham S, Wang M-J, Lee F, Chickermane V, Keller BL et al. Test and debug strategy for TSMC CoWoS® stacking process‐based heterogeneous 3D‐IC: a silicon study. In Franzon PD, Marinissen EJ, Bakir MS, editors, Handbook of 3D integration: volume 4: design, test, and thermal management. Weinheim: Wiley-VCH Verlag. 2019. p. 325-346 https://doi.org/10.1002/9783527697052.ch15