Test access architecture for TSV-based 3D stacked ICS

E.J. Marinissen; J. Verbree; M. Konijnenburg; C.-C. Chi

Test access architecture for TSV-based 3D stacked ICS

E.J. Marinissen (Inventor), J. Verbree (Inventor), M. Konijnenburg (Inventor), C.-C. Chi (Inventor)

Research output: Patent › Patent publication

Abstract

A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

Original language	English
Patent number	WO2011117418
IPC	G01R 31/ 3185 A I
Priority date	20/09/10
Publication status	Published - 29 Sept 2011
Externally published	Yes

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title = "Test access architecture for TSV-based 3D stacked ICS",

abstract = "A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.",

author = "E.J. Marinissen and J. Verbree and M. Konijnenburg and C.-C. Chi",

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T1 - Test access architecture for TSV-based 3D stacked ICS

AU - Marinissen, E.J.

AU - Verbree, J.

AU - Konijnenburg, M.

AU - Chi, C.-C.

PY - 2011/9/29

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N2 - A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

AB - A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

M3 - Patent publication

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ER -

Test access architecture for TSV-based 3D stacked ICS

Abstract

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