Test access architecture for TSV-based 3D stacked ICS

E.J. Marinissen (Inventor), J. Verbree (Inventor), M. Konijnenburg (Inventor), C.-C. Chi (Inventor)

Research output: PatentPatent publication


A test access architecture is presented for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external l/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

Original languageEnglish
Patent numberWO2011117418
IPCG01R 31/ 3185 A I
Priority date20/09/10
Publication statusPublished - 29 Sept 2011
Externally publishedYes


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