Test access architecture for interposer-based 3D die stacks

E.J. Marinissen (Inventor), C.-C. Chi (Inventor)

Research output: PatentPatent publication

Abstract

A semiconductor interposer (40) for stacking on top thereof at least two die towers each comprising at least one die (Die 1, Die 2, Die 3), and for interconnecting the die towers by means of at least functional wires (w01, w21,, w32) in the interposer (40), comprises test circuitry for post-bond testing of the dies (Die 1, Die 2, Die 3) and of electrical interconnections between the die towers and the interposer (40). The test circuitry comprises a primary port (Port 0) to external I/Os, or to a die different from the dies of the die towers and a plurality of secondary ports (Port 1, Port 2, Port 3) for stacking the at least two die towers onto. There is a data signal path within the interposer (40) between the primary port (Port 0) and at least one of the plurality of secondary ports (Port 1, Port 2, Port 3). At least one functional wire in the interposer (40) is re-used as part of the test circuitry.

Original languageEnglish
Patent numberWO2013004836
IPCG01R 31/ 3185 A I
Priority date6/07/11
Publication statusPublished - 10 Jan 2013
Externally publishedYes

Fingerprint

Dive into the research topics of 'Test access architecture for interposer-based 3D die stacks'. Together they form a unique fingerprint.

Cite this