In this chapter, we concentrate on technological quantitative pointers for adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in modem CMOS digital designs. In particular, we will present the power savings that can be expected, the power-delay trade-offs that can be made, and the implications of these techniques on present semiconductor technologies. Furthermore, we will show to which extent process-dependent performance compensation can be used. Our presentation is a result of extensive analyses based on test-circuits fabricated in the state-of-the-art CMOS processes. Experimental results have been obtained for both 9Onm and 65nm CMOS technology nodes.
|Title of host publication||Adaptive Techniques for Dynamic Processor Optimization : Theory and Practice|
|Editors||A. Wang, S. Naffziger|
|Place of Publication||Berlin|
|Number of pages||23|
|Publication status||Published - 2008|
Meijer, M., & Pineda de Gyvez, J. (2008). Technological boundaries of voltage and frequency scaling for power performance tuning. In A. Wang, & S. Naffziger (Eds.), Adaptive Techniques for Dynamic Processor Optimization : Theory and Practice (pp. 25-47). Springer. https://doi.org/10.1007/978-0-387-76472-6_2