Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip.

P. Poplavko; T. Basten; M.J.G. Bekooij; J. Meerbergen, van; B. Mesman

Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip.

P. Poplavko
, T. Basten
, M.J.G. Bekooij
, J. Meerbergen, van
, B. Mesman

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems.
Place of Publication	San Jose, CA, USA
Publisher	ACN
Pages	63-72
ISBN (Print)	1-58113-676-5
Publication status	Published - 2003
Event	International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2003) - San Jose, United States Duration: 30 Oct 2003 → 1 Nov 2003

Conference

Conference	International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2003)
Country/Territory	United States
City	San Jose
Period	30/10/03 → 1/11/03
Other	CASES 2003, San Jose, CA, USA

Cite this

@inproceedings{e2b081544a744e899af5c05d67464444,

title = "Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip.",

author = "P. Poplavko and T. Basten and M.J.G. Bekooij and \{Meerbergen, van\}, J. and B. Mesman",

year = "2003",

language = "English",

isbn = "1-58113-676-5",

pages = "63--72",

booktitle = "Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems.",

publisher = "ACN",

note = "International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2003) ; Conference date: 30-10-2003 Through 01-11-2003",

}

Poplavko, P, Basten, T, Bekooij, MJG, Meerbergen, van, J & Mesman, B 2003, Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip. in Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems.. ACN, San Jose, CA, USA, pp. 63-72, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2003), San Jose, California, United States, 30/10/03.

Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip. / Poplavko, P.; Basten, T.; Bekooij, M.J.G. et al.
Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems.. San Jose, CA, USA: ACN, 2003. p. 63-72.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks -on-Chip.

AU - Poplavko, P.

AU - Basten, T.

AU - Bekooij, M.J.G.

AU - Meerbergen, van, J.

AU - Mesman, B.

PY - 2003

Y1 - 2003

M3 - Conference contribution

SN - 1-58113-676-5

SP - 63

EP - 72

BT - Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems.

PB - ACN

CY - San Jose, CA, USA

T2 - International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2003)

Y2 - 30 October 2003 through 1 November 2003

ER -