Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systems

L. Zhang, R. Schneider, D. Goswami, S. Chakraborty

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

33 Citations (Scopus)

Abstract

In this paper, we study time-triggered distributed systems where periodic application tasks are mapped onto different end stations (processing units) communicating over a switched Ethernet network. We address the problem of application level (i.e., both task- and network-level) schedule synthesis and optimization. In this context, most of the recent works [10], [11] either focus on communication schedule or consider a simplified task model. In this work, we formulate the co-synthesis problem of task and communication schedules as a Mixed Integer Programming (MIP) model taking into account a number of Ethernet-specific timing parameters such as interframe gap, precision and synchronization error. Our formulation is able to handle one or multiple timing objectives such as application response time, end-to-end delay and their combinations. We show the applicability of our formulation considering an industrial size case study using a number of different sets of objectives. Further, we show that our formulation scales to systems with reasonably large size.
Original languageEnglish
Title of host publicationAsia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2014, Yokohama, Japan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages119-124
Number of pages6
ISBN (Electronic)978-1-4799-2816-3
DOIs
Publication statusPublished - 2014
Event2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore, Singapore
Duration: 20 Jan 201423 Jan 2014

Conference

Conference2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)
CountrySingapore
CitySingapore
Period20/01/1423/01/14

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  • Cite this

    Zhang, L., Schneider, R., Goswami, D., & Chakraborty, S. (2014). Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systems. In Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2014, Yokohama, Japan (pp. 119-124). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASPDAC.2014.6742876