Systematic extraction of critical areas from IC layouts

J. Pineda de Gyvez, J.A.G. Jess

Research output: Chapter in Book/Report/Conference proceedingChapterAcademic

Original languageEnglish
Title of host publicationDefect and Fault Tolerance in VLSI System. (Volume 3)
EditorsC.H. Stapper, V.K. Jain, G. Saucier
Place of PublicationNew York
PublisherPlenum Press
Publication statusPublished - 1990

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