TY - JOUR
T1 - System level receiver design for minimum sensitivity to process variations
AU - Sakian Dezfuli, P.
AU - Mahmoudi, R.
AU - Roermund, van, A.H.M.
PY - 2011
Y1 - 2011
N2 - A system-level design methodology is proposed to reduce the sensitivity of an integrated zero-IF receiver, including the analog-to-digital converter, to performance variations of its components due to process spreading. Describing each stage of the receiver by three parameters of voltage gain, noise, and nonlinearity, whose variations represent all lower-level sources of variability, the sensitivity of the overall performance to the variations of these parameters is calculated. Three design approaches are proposed, analyzed, and compared for reducing these sensitivities. Statistical and corner simulations are performed to con¿rm the validity of the proposed guidelines showing signi¿cant improvement in the yield of the designs.
AB - A system-level design methodology is proposed to reduce the sensitivity of an integrated zero-IF receiver, including the analog-to-digital converter, to performance variations of its components due to process spreading. Describing each stage of the receiver by three parameters of voltage gain, noise, and nonlinearity, whose variations represent all lower-level sources of variability, the sensitivity of the overall performance to the variations of these parameters is calculated. Three design approaches are proposed, analyzed, and compared for reducing these sensitivities. Statistical and corner simulations are performed to con¿rm the validity of the proposed guidelines showing signi¿cant improvement in the yield of the designs.
U2 - 10.1109/TCSI.2011.2123790
DO - 10.1109/TCSI.2011.2123790
M3 - Article
SN - 1549-8328
VL - 58
SP - 2296
EP - 2307
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 10
ER -