System-level interconnect architecture exploration for custom memory organizations

T. Meeuwen, van, A. Vandecappelle, A. Zelst, van, F. Catthoor, D.T.M.L. Verkest

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    12 Citations (Scopus)

    Abstract

    For data dominated applications, power consumption and memory bandwidth bottlenecks can be significantly alleviated with a custom memory organization. However, this potentially entails complex memory interconnections and a large routing overhead. This is undesirable for area cost, power consumption, and layout design complexity. By exploiting time-multiplexing opportunities over the long memory buses, this overhead can be significantly reduced. This paper proposes a system-level methodology for automated exploration of the interconnect architecture, which finds the optimal trade-off points for memory bus time-multiplexing. Experiments performed on real-life applications using our prototype tool show that even for very distributed memory organizations, the interconnect complexity can be significantly reduced to a cost-efficient, manageable level.
    Original languageEnglish
    Title of host publication14th International Symposium on System Synthesis, 2001
    Place of PublicationPiscataway
    PublisherInstitute of Electrical and Electronics Engineers
    Pages13-18
    ISBN (Print)1-58113-418-5
    DOIs
    Publication statusPublished - 2001
    EventInternational Symposium on System Synthesis, Montreal, Canada; 2001-09-30; 2001-10-03 -
    Duration: 30 Sep 20013 Oct 2001

    Conference

    ConferenceInternational Symposium on System Synthesis, Montreal, Canada; 2001-09-30; 2001-10-03
    Period30/09/013/10/01

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