Abstract
Abstract—JEDEC recently introduced its new standard for 3D-
stacked Wide I/O DRAM memories, which defines their archi-
tecture, design, features and timing behavior. With improved
performance/power trade-offs over previous generation DRAMs,
Wide I/O DRAMs provide an extremely energy-efficient green
memory solution required for next-generation embedded and high-
performance computing systems. With both industry and academia
pushing to evaluate and employ these highly anticipated memories,
there is an urgent need for an accurate power model targeting
Wide I/O DRAMs that enables their efficient integration and energy
management in DRAM stacked SoC architectures.
In this paper, we present the first system-level power model of
3D-stacked Wide I/O DRAM memories that is almost as accurate
as detailed circuit-level power models of 3D-DRAMs. To verify
its accuracy, we experimentally compare its power and energy
estimates for different memory workloads and operations against
those of a circuit-level 3D-DRAM power model and show less than
2% difference between the two sets of estimates.
Original language | English |
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Title of host publication | Proceedings of Design, Automation & Test in Europe & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France |
Editors | K. Preas |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 236-241 |
ISBN (Print) | 978-1-4673-5071-6 |
DOIs | |
Publication status | Published - 2013 |
Event | 16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) - Grenoble, France Duration: 18 Mar 2013 → 22 Mar 2013 Conference number: 16 https://www.date-conference.com/date13/ |
Conference
Conference | 16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) |
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Abbreviated title | DATE 2013 |
Country/Territory | France |
City | Grenoble |
Period | 18/03/13 → 22/03/13 |
Other | |
Internet address |