Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azemard, Aida Todri-Sanial

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

12 Citations (Scopus)

Abstract

Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-Adiabatic CMOS pipeline.

Original languageEnglish
Title of host publication2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers
Pages1-6
Number of pages6
ISBN (Electronic)9781538615539
DOIs
Publication statusPublished - 28 Nov 2017
Externally publishedYes
Event2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Washington, United States
Duration: 8 Nov 20179 Nov 2017

Conference

Conference2017 IEEE International Conference on Rebooting Computing, ICRC 2017
Country/TerritoryUnited States
CityWashington
Period8/11/179/11/17

Bibliographical note

Publisher Copyright:
©2017 IEEE.

Keywords

  • Adiabatic Logic
  • Energy Efficiency
  • Power-Clock Supply
  • Resonant Power Supply
  • Reversible Power Supply

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