Switched-capacitor power converters are interesting candidates to realize integrated power converters with acceptable power efficiencies. Depending on the input and output voltage ranges to be accommodated at a desired efficiency, certain voltage conversion ratio(s) need(s) to be implemented. Though the theoretical minimum number of floating capacitors to realize a desired voltage conversion ratio is known, how to actually synthesize the corresponding topologies and what impact these topologies have on circuit performance is less trivial. Besides two-clock-phase topologies, multiple-clock-phase topologies have recently been introduced. This paper gives an overview of various methods to implement desired voltage conversion ratios with two or multiple clock phases and compares their performance under given boundary conditions.
|Title of host publication||Wideband continuous-time ΣΔ ADCs, automotive electronics, and power management: Advances in Analog Circuit Design 2016: part III|
|Editors||A Baschirotto, P. Harpe, K.A.A. Makinwa|
|Publication status||Published - 2016|