Supervisory Control Synthesis of Timed Automata Using Forcible Events

This paper presents an algorithm for synthesizing a supervisor for timed automata (TA) using the conventional supervisory control theory. The algorithm is directly applicable to TA without explicit transformation into finite automata, and iteratively strengthens the guards of edges labeled by controllable events and invariants of locations where the progression of time can be preempted by forcible events. The synthesized supervisor, also a TA, is controllable, maximally permissive, and guarantees a non-blocking and safe supervised plant. The use of real-valued clocks in TA makes it a practical modeling framework, however, the infinite state space brings challenges. The proposed algorithm addresses these by providing a synthesis method that avoids the state-space explosion of finite automata and the loss of information that can result from abstraction of real-time values.