Static memory devices

L. Elvira Villagra; R.I.M.P. Meijer; J. Pineda de Gyvez

Static memory devices

L. Elvira Villagra (Inventor)
, R.I.M.P. Meijer (Inventor)
, J. Pineda de Gyvez (Inventor)

Electronic Systems

Research output: Patent › Patent publication

Abstract

A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Original language	English
Patent number	US8107288 B2
Publication status	Published - 31 Jan 2012

Cite this

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title = "Static memory devices",

abstract = "A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.",

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note = "US8107288 B2",

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T1 - Static memory devices

AU - Elvira Villagra, L.

AU - Meijer, R.I.M.P.

AU - Pineda de Gyvez, J.

PY - 2012/1/31

Y1 - 2012/1/31

N2 - A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

AB - A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

UR - http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=8107288B2&KC=B2&FT=D&ND=4&date=20120131&DB=EPODOC&locale=nl_NL

M3 - Patent publication

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ER -

Static memory devices

Abstract

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