Abstract
In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - Design, Automation and Test in Europe, DATE 2014, 24-28 March 2014, Dresden, Germany |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-6 |
| ISBN (Electronic) | 9783981537024 |
| ISBN (Print) | 978-1-4799-3297-9 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | 17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) - ICC, Dresden, Germany Duration: 24 Mar 2014 → 28 Mar 2014 Conference number: 17 https://www.date-conference.com/date14/ |
Conference
| Conference | 17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) |
|---|---|
| Abbreviated title | DATE 2014 |
| Country/Territory | Germany |
| City | Dresden |
| Period | 24/03/14 → 28/03/14 |
| Internet address |
Keywords
- Gate delay variation
- Intra-die variation
- Local variation
- Mismatch variation
- Standard cell library tuning
- Statistical library
- Variability tolerant design