Standard cell library tuning for variability tolerant designs

S. Fabrie, J. Diego Echeverri, M. Vertreg, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)


In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem due to mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014, 24-28 March 2014, Dresden, Germany
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Electronic)9783981537024
ISBN (Print)978-1-4799-3297-9
Publication statusPublished - 2014
Event17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) - ICC, Dresden, Germany
Duration: 24 Mar 201428 Mar 2014
Conference number: 17


Conference17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014)
Abbreviated titleDATE 2014
City Dresden
Internet address


  • Gate delay variation
  • Intra-die variation
  • Local variation
  • Mismatch variation
  • Standard cell library tuning
  • Statistical library
  • Variability tolerant design


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