Standard cell based memory compiler for near/sub-threshold operation

Voltage scaling to near/sub-threshold region is commonly used to achieve energy-efficient operation in digital circuits. However, the voltage-scaling potential of traditional 6T SRAM memories is limited by reliability problems. For small size memories, designers tend to a use latch/flip-flop based register file which brings relatively high area overhead, high delay penalty, and power overhead. In this work, a standard-cell based memory (SCM) compiler is presented to automatically generate a 12T OAI based SCM for multiple CMOS technologies operating in near/sub-threshold region. The SCM compiler utilizes Python-MyHDL for RTL and constraint generation. The timing and floor-plan constraints are generated based on user specified technology, memory size, and memory shape inputs. The power, area, energy per access, read delay, and write delays are evaluated for the generated memories of different sizes and shapes. The proposed 12T OAI based SCM achieves average speed-up of 28%/39% in write delay and average speed-up of 25%/19% in read delay when compared to D-latch/flip-flop based memories in a 28-nm FDSOI technology. Furthermore, 41% reduction in energy per access and 33% area saving are obtained, compared to a recently published SCM design in 40-nm CMOS technology [1].