SPINE : from C loop-nests to highly efficient accelerators using algorithmic species

M. Wijtvliet, S.D. Fernando, H. Corporaal

Research output: Contribution to conferencePaper

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Abstract

In modern embedded systems, heterogeneous architectures are crucial in achieving desired performance requirements under area and energy constraints. Many of these systems combine a multi-processor system-on-chip and a Field Programmable Gate Array to enable hardware acceleration. Although the introduction of High-Level Synthesis significantly reduced the complexity of utilizing these systems, a programmer is still required to have expert knowledge of both the High-Level Synthesis tool and the target hardware and to perform time consuming manual iterations to achieve efficient implementations. In this paper we present SPINE, a design flow for automatic generation of efficient hardware accelerators based on Algorithmic Species. SPINE allows the designer to focus on the algorithm by automatically applying hardware specific optimizations and parallelization techniques to the design. As a case study, we present a design space exploration of nine different loop-nests used in image processing kernels and show how SPINE rapidly generates multiple area-performance trade-offs. Furthermore, we compare our results the state of the art and show that SPINE is a promising direction for accelerator generation as the average performance and area improvement with SPINE are respectively 107% and 75% over the state of the art.
Original languageEnglish
Pages1-6
Number of pages6
DOIs
Publication statusPublished - 2 Sep 2015
Event25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom - London, United Kingdom
Duration: 2 Sep 20154 Sep 2015
http://www.fpl2015.org/

Conference

Conference25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom
Abbreviated titleFPL 2015
CountryUnited Kingdom
CityLondon
Period2/09/154/09/15
Internet address

Fingerprint

Particle accelerators
Hardware
Embedded systems
Field programmable gate arrays (FPGA)
Image processing
High level synthesis

Keywords

  • Accelerators
  • FPGA
  • High Level Synthesis

Cite this

Wijtvliet, M., Fernando, S. D., & Corporaal, H. (2015). SPINE : from C loop-nests to highly efficient accelerators using algorithmic species. 1-6. Paper presented at 25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom, London, United Kingdom. https://doi.org/10.1109/FPL.2015.7294015
Wijtvliet, M. ; Fernando, S.D. ; Corporaal, H. / SPINE : from C loop-nests to highly efficient accelerators using algorithmic species. Paper presented at 25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom, London, United Kingdom.6 p.
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Wijtvliet, M, Fernando, SD & Corporaal, H 2015, 'SPINE : from C loop-nests to highly efficient accelerators using algorithmic species', Paper presented at 25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom, London, United Kingdom, 2/09/15 - 4/09/15 pp. 1-6. https://doi.org/10.1109/FPL.2015.7294015

SPINE : from C loop-nests to highly efficient accelerators using algorithmic species. / Wijtvliet, M.; Fernando, S.D.; Corporaal, H.

2015. 1-6 Paper presented at 25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom, London, United Kingdom.

Research output: Contribution to conferencePaper

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AU - Fernando, S.D.

AU - Corporaal, H.

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AB - In modern embedded systems, heterogeneous architectures are crucial in achieving desired performance requirements under area and energy constraints. Many of these systems combine a multi-processor system-on-chip and a Field Programmable Gate Array to enable hardware acceleration. Although the introduction of High-Level Synthesis significantly reduced the complexity of utilizing these systems, a programmer is still required to have expert knowledge of both the High-Level Synthesis tool and the target hardware and to perform time consuming manual iterations to achieve efficient implementations. In this paper we present SPINE, a design flow for automatic generation of efficient hardware accelerators based on Algorithmic Species. SPINE allows the designer to focus on the algorithm by automatically applying hardware specific optimizations and parallelization techniques to the design. As a case study, we present a design space exploration of nine different loop-nests used in image processing kernels and show how SPINE rapidly generates multiple area-performance trade-offs. Furthermore, we compare our results the state of the art and show that SPINE is a promising direction for accelerator generation as the average performance and area improvement with SPINE are respectively 107% and 75% over the state of the art.

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Wijtvliet M, Fernando SD, Corporaal H. SPINE : from C loop-nests to highly efficient accelerators using algorithmic species. 2015. Paper presented at 25th International Conference on Field Programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, United Kingdom, London, United Kingdom. https://doi.org/10.1109/FPL.2015.7294015