SparseRC : sparsity preserving model reduction for RC circuits with many terminals

R. Ionutiu, J. Rommes, W.H.A. Schilders

Research output: Book/ReportReportAcademic

28 Citations (Scopus)
108 Downloads (Pure)


A novel model order reduction (MOR) method for multi-terminal RC circuits is proposed: SparseRC. Specifically tailored to systems with many terminals, SparseRC employs graph-partitioning and fill-in reducing orderings to improve sparsity during model reduction, while maintaining accuracy via moment matching. The reduced models are easily converted to their circuit representation. These contain much fewer nodes and circuit elements than otherwise obtained with conventional MOR techniques, allowing faster simulations at little accuracy loss.
Original languageEnglish
Place of PublicationEindhoven
PublisherTechnische Universiteit Eindhoven
Number of pages14
Publication statusPublished - 2011

Publication series

ISSN (Print)0926-4507


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