Solutions to multiple probing challenges for test access to multi-die stacked integrated circuits

Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)


Multi-die stacked ICs are getting increasing traction in the market, fueled by innovations in wafer processing technologies (e.g., vertical inter-die and intra-die connections), stack assembly, and advanced packaging approaches (e.g., wafer-level packaging). Given the non-perfect nature of their manufacturing processes, these stacked ICs (SICs) need all to be individually tested for manufacturing defects in an effective, yet efficient manner. This paper discusses a handful of probing challenges specific to such SICs and their solutions: probing ultra-thin wafers on a flexible tape on extra-large tape frames, probing on large arrays of dense micro-bumps, analyzing probe-to-pad alignment (PTPA) accuracy contributions from probe station and probe card on the basis of probe mark images, and efficient auto-correction of individual misalignments of singulated dies or die stacks on tape. The paper concludes with a real-life case study, in which most of the discussed challenges and solutions are combined.

Original languageEnglish
Title of host publication2018 IEEE International Test Conference (ITC)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages10
ISBN (Electronic)978-1-5386-8382-8
ISBN (Print)978-1-5386-8383-5
Publication statusPublished - 30 Oct 2018
Event49th IEEE International Test Conference, ITC 2018 - Phoenix, United States
Duration: 29 Oct 20181 Nov 2018


Conference49th IEEE International Test Conference, ITC 2018
Country/TerritoryUnited States


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