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Skeleton-based automatic parallelization of image processing algorithms for GPUs

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Abstract

Graphics Processing Units (GPUs) are becoming increasingly important in high performance computing. To maintain high quality solutions, programmers have to efficiently parallelize and map their algorithms. This task is far from trivial, leading to the necessity to automate this process. In this paper, we present a technique to automatically parallelize and map sequential code on a GPU, without the need for code-annotations. This technique is based on skeletonization and is targeted at image processing algorithms. Skeletonization separates the structure of a parallel computation from the algorithm's functionality, enabling efficient implementations without requiring architecture knowledge from the programmer. We define a number of skeleton classes, each enabling GPU specific parallelization techniques and optimizations, including automatic thread creation, on-chip memory usage and memory coalescing. Recently, similar skeletonization techniques have been applied to GPUs. Our work uses domain specific skeletons and a finer-grained classification of algorithms. Comparing skeleton-based parallelization to existing GPU code generators in general, we potentially achieve a higher hardware efficiency by enabling algorithm restructuring through skeletons. In a set of benchmarks, we show that the presented skeleton-based approach generates highly optimized code, achieving high data throughput. Additionally, we show that the automatically generated code performs close or equal to manually mapped and optimized code. We conclude that skeleton-based parallelization for GPUs is promising, but we do believe that future research must focus on the identification of a finer-grained and complete classification.
Original languageEnglish
Title of host publicationProceedings of the 11th International COnference on Embedded Computer Systems, Architectures, Modeling and Simulation, 18-21 July 2011, Samos, Greece
Place of PublicationSamos, Greece
PublisherInstitute of Electrical and Electronics Engineers
Pages25-32
ISBN (Print)978-1-4577-0802-2
DOIs
Publication statusPublished - 2011
Eventconference; SAMOS X1, Samos, Greece; 2011-07-18; 2011-07-21 -
Duration: 18 Jul 201121 Jul 2011

Conference

Conferenceconference; SAMOS X1, Samos, Greece; 2011-07-18; 2011-07-21
Period18/07/1121/07/11
OtherSAMOS X1, Samos, Greece

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