SIMD with delay line in instruction bus

H. Fatemi (Inventor), B. Mesman (Inventor), H. Corporaal (Inventor), T. Basten (Inventor), R.P. Kleihorst (Inventor)

Research output: PatentPatent publication

Abstract

The ID discloses a SIMD processor array havint two segmented unidirectional busses for communicating data between the various processing elements (PEs). In addition, the instruction bus of the PEs comprises delay elements to facilitate the execution of instructions by different PEs at different points in time. In a preferred embodiment, the delay elements in the instruction bus may be bypassed to enable two operational modes of the SIMD: one mode in which all PEs simultaneously execute the same instruction and one mode in which the instructions are delayed from one PE to another. According to another aspect of the invention, a scheduler for such an SIMD architecture is provided for soloving data dependency conflicts by scheduling the full set of instructions for a given PE, and deriving the scheduling of all other PEs as a function of the appropriate delay from the schedule for the given PE
Original languageEnglish
Patent numberPH005781
Publication statusPublished - 19 Apr 2006

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Electric delay lines
Processing
Scheduling
Patents and inventions
Parallel processing systems

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Fatemi, H., Mesman, B., Corporaal, H., Basten, T., & Kleihorst, R. P. (2006). SIMD with delay line in instruction bus. (Patent No. PH005781).
Fatemi, H. (Inventor) ; Mesman, B. (Inventor) ; Corporaal, H. (Inventor) ; Basten, T. (Inventor) ; Kleihorst, R.P. (Inventor). / SIMD with delay line in instruction bus. Patent No.: PH005781.
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abstract = "The ID discloses a SIMD processor array havint two segmented unidirectional busses for communicating data between the various processing elements (PEs). In addition, the instruction bus of the PEs comprises delay elements to facilitate the execution of instructions by different PEs at different points in time. In a preferred embodiment, the delay elements in the instruction bus may be bypassed to enable two operational modes of the SIMD: one mode in which all PEs simultaneously execute the same instruction and one mode in which the instructions are delayed from one PE to another. According to another aspect of the invention, a scheduler for such an SIMD architecture is provided for soloving data dependency conflicts by scheduling the full set of instructions for a given PE, and deriving the scheduling of all other PEs as a function of the appropriate delay from the schedule for the given PE",
author = "H. Fatemi and B. Mesman and H. Corporaal and T. Basten and R.P. Kleihorst",
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Fatemi, H, Mesman, B, Corporaal, H, Basten, T & Kleihorst, RP 2006, SIMD with delay line in instruction bus, Patent No. PH005781.

SIMD with delay line in instruction bus. / Fatemi, H. (Inventor); Mesman, B. (Inventor); Corporaal, H. (Inventor); Basten, T. (Inventor); Kleihorst, R.P. (Inventor).

Patent No.: PH005781.

Research output: PatentPatent publication

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T1 - SIMD with delay line in instruction bus

AU - Fatemi, H.

AU - Mesman, B.

AU - Corporaal, H.

AU - Basten, T.

AU - Kleihorst, R.P.

PY - 2006/4/19

Y1 - 2006/4/19

N2 - The ID discloses a SIMD processor array havint two segmented unidirectional busses for communicating data between the various processing elements (PEs). In addition, the instruction bus of the PEs comprises delay elements to facilitate the execution of instructions by different PEs at different points in time. In a preferred embodiment, the delay elements in the instruction bus may be bypassed to enable two operational modes of the SIMD: one mode in which all PEs simultaneously execute the same instruction and one mode in which the instructions are delayed from one PE to another. According to another aspect of the invention, a scheduler for such an SIMD architecture is provided for soloving data dependency conflicts by scheduling the full set of instructions for a given PE, and deriving the scheduling of all other PEs as a function of the appropriate delay from the schedule for the given PE

AB - The ID discloses a SIMD processor array havint two segmented unidirectional busses for communicating data between the various processing elements (PEs). In addition, the instruction bus of the PEs comprises delay elements to facilitate the execution of instructions by different PEs at different points in time. In a preferred embodiment, the delay elements in the instruction bus may be bypassed to enable two operational modes of the SIMD: one mode in which all PEs simultaneously execute the same instruction and one mode in which the instructions are delayed from one PE to another. According to another aspect of the invention, a scheduler for such an SIMD architecture is provided for soloving data dependency conflicts by scheduling the full set of instructions for a given PE, and deriving the scheduling of all other PEs as a function of the appropriate delay from the schedule for the given PE

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Fatemi H, Mesman B, Corporaal H, Basten T, Kleihorst RP, inventors. SIMD with delay line in instruction bus. PH005781. 2006 Apr 19.