An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.
|Publication status||Published - 11 Apr 2013|
Bibliographical noteAlso published as:
Kampen, van, D., Berkel, van, C. H., Goossens, S. L. M., Kloosterhuis, W. E. H., & Zissulecsu-Ianculescu, C. (2013). SIMD memory circuit and methodology to support upsampling, downsampling and transposition. (Patent No. US20130091339).