Silicon based system-in-package: Breakthroughs in miniaturization and 'nano'-integration supported by very high quality passives and system level design tools

The very large development of home and domestic electronic appliances as well as portable devices has led the microelectronics industry to evolve in two complementary directions: "More Moore" with the continuous race towards extremely small dimensions, hence the development of SoCs (System on Chip) and more recently a new direction that we could name "More than Moore" with the integration of devices that were laying outside the chips and here the creation of SiPs (System in Package). These two approaches are not in competition with one another: this paper will show some examples of integrated nano-systems that use several SoCs. The technology we have developed is called Silicon-Based System in Package. The first products using this technology are now in volume production and used mainly in the field of wireless communication. This new technology relies on four pillars. Passive integration is the first: very efficient and high quality factor capacitors and inductors have been integrated, allowing the creation of complete modules including active devices, filters and decoupling capacitors. High-density MOS capacitors with 1-1000 nF capacitance, and as high values as 25-250+ nF/mm² specific capacitance have been fabricated in 150 mm diameter Si-wafers, containing over 1 billion macropores. Typically an ESR less than 100 mΩ and an ESL less than 25 pH were found for capacitors over 10 nF. This novel concept is an important step forward in improving the stability of power-amplifier modules by replacing conventional SMD technology. Whereas generations with capacitor densities of up to 100 nF/mm² will be using "conventional" materials and structures, the next steps in the roadmap will call for new 3D structures and materials such as high-k dielectrics. The second element is advanced packaging. New technologies, such as the assembly of silicon chips onto other silicon chips, also named "double flip-chip" have been developed. This has been made possible thanks to the combination of the most advanced microbumping and die placement techniques. In addition to a tremendous reduction of size (up to a factor of 10 to 20) these techniques have also brought a better repeatability of system performance. The third element has been the development of design tools that allow a seamless system design for engineers used to IC design tools and flows. Our Design Environment allows codesign of multiple-technologies chips and their integration in a single system. This IC-like Design Environment has greatly contributed to the adoption of the technology. Testing is the fourth element and is one of the economical enablers of the technology. The key words are: "Known-Good-Die", RF test, system test, etc. Some innovative RF probing and full on-wafer subsystem testing will be shown. Even though efficient testing is not vital for the technical feasibility of this system integration, it becomes very quickly one of the most important enablers, especially when we deal with very high volumes of production. The conclusion of the paper will be an open door to the future. Some innovations like the integration of solid state lighting devices or even energy storage devices inside our SiPs will be presented.