Abstract
A new type of sigma–delta modulator that operates
in a special mode named limit-cycle mode (LCM) is proposed. In
this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital–analog converter waveform asymmetry and a higher tolerance to clock imperfections
The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.
Original language | English |
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Pages (from-to) | 399-403 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 53 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2006 |