Sigma delta feedback DAC architectures for high accuracy and extremely low charge transfer

Sigma delta ADCs (SD-ADC) are often the preferred ADCs of choice in sensor interfacing applications due to their high achievable absolute accuracy. Constraints such as low power and limited area often dictate minimum front-end hardware, thereby limiting options for pre-processing stages. Processing very small input signals requires that the magnitudes of the signals at the input summing node match. Given that often the sensor output current is of extremely low magnitude, the feedback DAC also has to transfer extremely small charges (order of a few femto-coulombs). Such constraints challenge the limits of existing process technologies. This paper investigates single bit feedback DAC architectures tailored specifically for very low charge transfers. Switched capacitor DACs are a viable means of transferring discrete charge packets accurately. Various DAC structures are compared using criteria such as absolute charge transfer error, effect of parasitic capacitances and the output referred noise. Accuracy of the feedback DAC is a major bottle-neck in the overall accuracy of the SD-ADC. The accuracy of the SD-ADC is compared for different feedback DAC structures. DAC structures are individually simulated using Spectre for 0.13um 3.3V standard CMOS technology. Based on circuit simulations, the feedback DAC is modeled in MATLAB as a combination of a `gain' block, `offset' error, additive noise and delay. A 1-bit 2nd order CT-SDM with the DAC model in the feedback path is used as a test vehicle and is simulated in MATLAB for accuracy calculations.