Sigma-delta ADC clock jitter in digitally implemented receiver architectures

Paul T.M. van Zeijl; Robert H.M. van Veldhoven; Peter A.C.M. Nuijten

doi:10.1109/ECWT.2006.280423

Sigma-delta ADC clock jitter in digitally implemented receiver architectures

Paul T.M. van Zeijl, Robert H.M. van Veldhoven, Peter A.C.M. Nuijten

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in ps_rms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.

Original language	English
Title of host publication	Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006
Publisher	Institute of Electrical and Electronics Engineers
Pages	16-18
Number of pages	3
ISBN (Print)	2-9600551-5-2
DOIs	https://doi.org/10.1109/ECWT.2006.280423
Publication status	Published - 15 Jan 2007
Externally published	Yes
Event	9th European Conference on Wireless Technology, ECWT 2006 - Manchester, United Kingdom Duration: 10 Sept 2006 → 12 Sept 2006

Conference

Conference	9th European Conference on Wireless Technology, ECWT 2006
Country/Territory	United Kingdom
City	Manchester
Period	10/09/06 → 12/09/06

Access to Document

10.1109/ECWT.2006.280423

Cite this

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title = "Sigma-delta ADC clock jitter in digitally implemented receiver architectures",

abstract = "The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in psrms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.",

author = "{van Zeijl}, {Paul T.M.} and {van Veldhoven}, {Robert H.M.} and Nuijten, {Peter A.C.M.}",

year = "2007",

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doi = "10.1109/ECWT.2006.280423",

language = "English",

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pages = "16--18",

booktitle = "Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "9th European Conference on Wireless Technology, ECWT 2006 ; Conference date: 10-09-2006 Through 12-09-2006",

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van Zeijl, PTM, van Veldhoven, RHM & Nuijten, PACM 2007, Sigma-delta ADC clock jitter in digitally implemented receiver architectures. in Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006., 4057426, Institute of Electrical and Electronics Engineers, pp. 16-18, 9th European Conference on Wireless Technology, ECWT 2006, Manchester, United Kingdom, 10/09/06. https://doi.org/10.1109/ECWT.2006.280423

Sigma-delta ADC clock jitter in digitally implemented receiver architectures. / van Zeijl, Paul T.M.; van Veldhoven, Robert H.M.; Nuijten, Peter A.C.M.
Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006. Institute of Electrical and Electronics Engineers, 2007. p. 16-18 4057426.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in psrms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.

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Sigma-delta ADC clock jitter in digitally implemented receiver architectures

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