Scheduling for register file energy minimization in explicit datapath architectures.

D. She, Y. He, B. Mesman, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

13 Citations (Scopus)
2 Downloads (Pure)


In modern processor architectures, the register file (RF) consumes considerable amount of the processor power. It is well known that by allowing software to have explicit fine-grained control over the datapath, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic, thereby minimizing the RF energy. However, it is important to make sure that the gain in RF is not cancelled out by the overhead due to the fine-grained datapath control, in particular, the deterioration of code density in conventional TTAs. In this paper, we analyze the potential of minimizing RF energy in MOVE-Pro, a TTA-based processor framework. We present a flexible compiler backend, which performs energy-aware instruction scheduling to push the limit of RF energy reduction. The experimental results show that with the proposed energy-aware compiler backend, MOVE-Pro is able to significantly reduce RF energy compared to its RISC/VLIW counterparts, by up to 80%. Meanwhile the code density of MOVE-Pro remains at the same level as its RISC/VLIW counterparts, allowing the energy saving in RF to be successfully transferred to total energy saving.
Original languageEnglish
Title of host publicationProceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) 2012, 12-16 March 2012, Dresden, Germany
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - ICC, Dresden, Germany
Duration: 12 Mar 201216 Mar 2012
Conference number: 15


Conference15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Abbreviated titleDATE 2012
Internet address


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