Analog Computation-In-Memory (CIM) architectures promise to bring to the edge the required compute and memory demands of TinyML applications while consuming extremely low power. However, the analog CIM paradigm is suitable for accelerating vector-matrix multiplication patterns alone, and the accuracy of the computation itself is stirred by the CIM device and its driving circuit non-idealities. Despite these practical constraints, CIM accelerators are often developed and evaluated in isolation without considering real-world system-level conditions, such as sharing system resources (host CPU, main-memory, and interconnect) for inter-layer pre/post-processing, data alignment, and data movement. These make it challenging to evaluate the energy, performance, area, and accuracy tradeoff for practical, end-to-end applications. To address this, we propose a first SoC level, gem5-based, open-source simulation framework for CIM accelerator design. It supports the modeling of hierarchical CIM accelerators for different device technologies and digital/mixed-signal driving circuit configurations, along with their non-ideal behaviour. The associated full-stack software provides APIs for (re-)configuring the CIM accelerator for offloading computations at the system level. To demonstrate some capabilities of the SACA, we carried out design space exploration on two representative TinyML tasks - Human Activity Recognition and CIFAR10 image classification. The results lead to optimal accelerator profiles and indicate a tradeoff between the energy, area, performance, and accuracy for different configurations.
|Title of host publication||DCIS 2022|
|Subtitle of host publication||Proceedings of the 37th Conference on Design of Circuits and Integrated Systems|
|Publisher||Institute of Electrical and Electronics Engineers|
|Number of pages||6|
|Publication status||Published - 2022|
|Event||37th Conference on Design of Circuits and Integrated Systems, DCIS 2022 - Pamplona, Spain|
Duration: 16 Nov 2022 → 18 Nov 2022
|Conference||37th Conference on Design of Circuits and Integrated Systems, DCIS 2022|
|Period||16/11/22 → 18/11/22|
Bibliographical noteFunding Information:
Research supported by EU Horizon 2020 Research and Innovation Program through MNEMOSENE project under Grant 780215.
- computation in memory