Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

A. Artes; J.L. Ayala; A.V. Sathanur; J. Huisken; F. Catthoor

doi:10.1109/VLSISoC.2011.6081635

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

A. Artes, J.L. Ayala, A.V. Sathanur, J. Huisken, F. Catthoor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.

Original language	Undefined
Title of host publication	2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)
Pages	136 -141
DOIs	https://doi.org/10.1109/VLSISoC.2011.6081635
Publication status	Published - 1 Oct 2011
Externally published	Yes

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Access to Document

10.1109/VLSISoC.2011.6081635

Cite this

@inproceedings{6adc9c1feac14ef8950c295b4898be80,

title = "Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications",

abstract = "Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.",

keywords = "buffer circuits, buffer circuits, computer power supplies, computer power supplies, dynamic energy consumption, dynamic energy consumption, dynamic workload applications, dynamic workload applications, embedded systems, embedded systems, energy budget distribution, energy budget distribution, instruction memory organization, instruction memory organization, leakage energy consumption, leakage energy consumption, memory architecture, memory architecture, post-layout simulations, post-layout simulations, power optimization, power optimization, run-time loop buffer controller, run-time loop buffer controller, run-time self-tuning banked loop buffer architecture, run-time self-tuning banked loop buffer architecture, single monolithic memory, single monolithic memory, total energy consumption, total energy consumption",

author = "A. Artes and J.L. Ayala and A.V. Sathanur and J. Huisken and F. Catthoor",

year = "2011",

month = oct,

day = "1",

doi = "10.1109/VLSISoC.2011.6081635",

language = "Niet gedefinieerd",

pages = "136 --141",

booktitle = "2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)",

}

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. / Artes, A.; Ayala, J.L.; Sathanur, A.V. et al.
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC). 2011. p. 136 -141.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

AU - Artes, A.

AU - Ayala, J.L.

AU - Sathanur, A.V.

AU - Huisken, J.

AU - Catthoor, F.

PY - 2011/10/1

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N2 - Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.

AB - Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.

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BT - 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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