Abstract
SIMD processors are increasingly used in embedded systems for multi-media applications because of their area- and energy-efficiency. Communication between the processing elements (PEs) in an SIMD processor has remained a cause of inefficiency however; the SIMD concept prescribes that all PEs communicate in the same clock cycle. Existing SIMD architectures solve this problem either by multi-hop communication (causing cycle overhead), or by a fully connected communication network (causing area overhead). To solve the communication bottleneck, we propose a reconfigurable SIMD architecture (RC-SIMD) with a set of delay-lines in the instruction bus, distributing the accesses to the communication network over time. We can (re-) configure the size and number of delay-lines, a specific configuration representing a trade-off between the number of clock cycles and the length of a clock period. Reconfiguration time is typically much less than 1% of the execution time of an algorithm, and the extra configuration hardware is less than 2%. Experiments show that our reconfigurable architecture achieves (on average) more than 10% performance improvement over a non-reconfigurable architecture
Original language | English |
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Title of host publication | Proceedings of the 20th International Parallel and Distributed Processing Symposium, 26-29 April 2006, Rhodes Island, Greece |
Place of Publication | Los Alamitos, USA |
Publisher | IEEE Computer Society |
Pages | 1-4 |
ISBN (Print) | 1-4244-0054-6 |
DOIs | |
Publication status | Published - 2006 |
Event | 20th IEEE International Parallel & Distributed Processing Symposium (IPDS 2006) - Rhodes Island, Greece Duration: 25 Apr 2006 → 29 Apr 2006 Conference number: 20 |
Conference
Conference | 20th IEEE International Parallel & Distributed Processing Symposium (IPDS 2006) |
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Abbreviated title | IPDS 2006 |
Country/Territory | Greece |
City | Rhodes Island |
Period | 25/04/06 → 29/04/06 |