Abstract
The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.
Original language | English |
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Pages (from-to) | 1776-1782 |
Number of pages | 7 |
Journal | IEEE Transactions on Electron Devices |
Volume | 48 |
Issue number | 8 |
DOIs | |
Publication status | Published - 1 Aug 2001 |
Externally published | Yes |
Keywords
- CMOS integrated circuits
- Modeling
- MOS devices
- Radio frequency